TDF8591TH datasheet(4/34 Pages) NXP

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TDF8591TH_1

Product data sheet

Rev. 01 — 5 March 2008

4 of 34

NXP Semiconductors

TDF8591TH

× 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D ampliﬁer

The TDF8591TH contains two independent ampliﬁer channels with a differential input

stage, high output power, high efﬁciency (90 %), low distortion and a low quiescent

current. The ampliﬁer channels can be connected in the following conﬁgurations:

• Mono Bridge-Tied Load (BTL) ampliﬁer

• Dual Single-Ended (SE) ampliﬁers

The TDF8591TH also contains circuits common to both channels such as the oscillator, all

reference sources, the mode functionality and a digital timing manager. For protection a

thermal foldback, temperature, current and voltage protection are built in.

6.2 Mode selection

The TDF8591TH can be switched in three operating modes via pin MODE:

• Standby mode; the ampliﬁers are switched off to achieve a very low supply current

• Mute mode; the ampliﬁers are switching idle (50 % duty cycle), but the audio signal at

the output is suppressed by disabling the VI-converter input stages

• Operating mode; the ampliﬁers are fully operational with output signal

The input stage (see Figure 1) contributes to the DC offset measured at the ampliﬁer

output. To avoid pop noise the DC output offset voltage should be increased gradually at a

mode transition from mute to operating, or vice versa, by limiting the dVMODE/dt on pin

MODE, resulting in a small dVO(offset)/dt for the DC output offset voltage. The required time

constant for a gradually increase of the DC output offset voltage between mute and

operating is generated via an RC network on pin MODE. An example of a switching circuit

for driving pin MODE is illustrated in Figure 3 and explained in Table 3.

Fig 3.

Example of mode selection circuit

Table 3.

Mode selection

closed

Standby mode

closed

open

Standby mode

open

closed

Mute mode

open

Operating mode

001aad836

5.6 k

Ω

5.6 k

Ω

5.6 V

5.6 k

Ω

MODE

SGND

100

µF

(10 V)

VDDP

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