PCF85321 datasheet(33/44 Pages) NXP

33 / 44 page

PCF8532_1

Product data sheet

Rev. 1 — 10 February 2009

33 of 44

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

Alternatively the schematic can be also constructed such that all the devices have OSC

pin connected to VDD and thus an external CLK being provided for the system (all devices

connected to the same external CLK).

A conﬁguration where SYNC is connected but all PCF8532 are using the internal clock

(OSC pin tied to VSS) is not recommended and may lead to display artefacts!

Table 19.

SYNC contact resistance

Number of devices

Maximum contact resistance

6000

Ω

3 to 5

2200

Ω

6 to 8

1200

Ω

(1) Is master (OSC connected to VSS).

(2) Is slave (OSC connected to VDD).

Fig 21. Cascaded conﬁguration with two PCF8532’s using the internal clock of the

master

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

CLK

OSC

SYNC

160 segment drives

4 backplanes

160/80/40

segment drives

LCD PANEL

(up to 2560

elements)

PCF8532

(1)

SA0

VSS

VDD

VLCD

VDD

VLCD

001aah855

SDA

SDAACK

SCL

SYNC

CLK

OSC

BP0 to BP3

(open-circuit)

SA0

PCF8532

(2)

BP0 to BP3

2CB

≤

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