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EP3C40 bảng dữ liệu(PDF) 15 Page - Altera Corporation

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Giải thích chi tiết về linh kiện  Cyclone III Device Data Sheet
PDF  34 Pages
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EP3C40 bảng dữ liệu(HTML) 15 Page - Altera Corporation

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Chapter 1: Cyclone III Device Data Sheet
1–15
Switching Characteristics
© January 2010
Altera Corporation
Cyclone III Device Handbook, Volume 2
Switching Characteristics
This section provides the performance characteristics of the core and periphery blocks
for Cyclone III devices. All data is final and is based on actual silicon characterization
and testing. These numbers reflect the actual performance of the device under
worst-case silicon process, voltage, and junction temperature conditions.
Core Performance Specifications
Clock Tree Specifications
Table 1–19 lists the clock tree specifications for Cyclone III devices.
PLL Specifications
Table 1–20 describes the PLL specifications for Cyclone III devices when operating in
the commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (–40°C to 100°C), and the automotive junction temperature range
(–40°Cto 125°C). For more information about PLL block, refer to “PLL Block” in
“Glossary” on page 1–27.
Table 1–19. Cyclone III Devices Clock Tree Performance
Device
Performance
Unit
C6
C7
C8
EP3C5
500
437.5
402
MHz
EP3C10
500
437.5
402
MHz
EP3C16
500
437.5
402
MHz
EP3C25
500
437.5
402
MHz
EP3C40
500
437.5
402
MHz
EP3C55
500
437.5
402
MHz
EP3C80
500
437.5
402
MHz
EP3C120
(1)
437.5
402
MHz
Note to Table 1–19:
(1) EP3C120 offered in C7, C8, and I7 grades only.
Table 1–20. Cyclone III Devices PLL Specifications (Note 1)
(Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
f
IN (2)
Input clock frequency
5
—
472.5
MHz
f
INPF D
PFD input frequency
5
—
325
MHz
f
VC O (3)
PLL internal VCO operating range
600
—
1300
MHz
f
INDUTY
Input clock duty cycle
40
—
60
%
t
INJITTER_C CJ (4)
Input clock cycle-to-cycle jitter
F
REF
≥ 100 MHz
—
—
0.15
UI
F
REF < 100 MHz
—
—
±750
ps
f
OUT_EXT (external clock output)
(2)
PLL output frequency
—
—
472.5
MHz



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