ZXLD1374

ZXLD1374

Document number: DS35032 Rev. 1 - 2

Page 25 of 35

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October 2010

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The PWM pin is designed to be driven by both 3.3V and 5V logic levels. It can be driven also by an open drain/collector

transistor. In this case the designer can either use the internal pull-up network or an external pull-up network in order to

speed-up PWM transitions, as shown in the Boost/ Buck-boost section.

Figure 43. PWM Dimming from Open Collector Switch

Figure 44. PWM Dimming from MCU

LED current can be adjusted digitally, by applying a low frequency PWM logic signal to the PWM pin to turn the controller on

and off. This will produce an average output current proportional to the duty cycle of the control signal. During PWM

operation, the device remains powered up and only the output switch is gated by the control signal.

The PWM signal can achieve very high LED current resolution. In fact, dimming down from 100% to 0, a minimum pulse

width of 5us can be achieved resulting in very high accuracy. While the maximum recommended pulse is for the PWM

signal is10ms.

Figure 45. PWM Dimming Minimum and Maximum Pulse