LTC2463CDDPBF datasheet(16/20 Pages) LINER

16 / 20 page

LTC2461/LTC2463

24613f

APPLICATIONS INFORMATION

to the point that signiﬁcant measurement errors exist.

Additionally, for some applications, increasing the RS• CIN

product too much may unacceptably attenuate the signal

at frequencies of interest.

For most applications, it is desirable to implement CIN as

a high-quality 0.1μF ceramic capacitor and to set RS ≤ 1k.

This capacitor should be located as close as possible to

the actual IN+, IN– or IN package pin. Furthermore, the

area encompassed by this circuit path, as well as the path

length, should be minimized.

In the case of a 2-wire sensor that is not remotely

grounded, it is desirable to split RS and place series

resistors in the ADC input line as well as in the sensor

ground return line, which should be tied to the ADC GND

pin using a star connection topology.

Figure 10 shows the measured LTC2463 INL vs Input

Voltage as a function of RS value with an input capacitor

CIN = 0.1μF.

In some cases, RScanbeincreasedabovetheseguidelines.

The input current is zero when the ADC is either in sleep

or I/O modes. Thus, if the time constant of the input RC

circuit

τ = RS • CIN, is of the same order of magnitude or

longer than the time periods between actual conversions,

then one can consider the input current to be reduced

correspondingly.

These considerations need to be balanced out by the input

signal bandwidth. The 3dB bandwidth ≈ 1/(2

πRSCIN).

Finally, if the recommended choice for CIN is unacceptable

for the user’s speciﬁc application, an alternate strategy is to

eliminate CIN and minimize CPAR and RS. In practical terms,

this conﬁguration corresponds to a low impedance sensor

directly connected to the ADC through minimum length

traces. Actual applications include current measurements

through low value sense resistors, temperature measure-

ments, low impedance voltage source monitoring, and so

on. The resultant INL vs VIN is shown in Figure 11. The

measurements of Figure 11 include a capacitor CPAR cor-

responding to a minimum sized layout pad and a minimum

width input trace of about 1 inch length.

Signal Bandwidth, Transition Noise and Noise

Equivalent Input Bandwidth

The LTC2461/LTC2463 include a sinc1 type digital ﬁlter

with the ﬁrst notch located at f0 = 60Hz. As such, the

3dB input signal bandwidth is 26.54Hz. The calculated

LTC2461/LTC2463 input signal attenuation vs frequency

over a wide frequency range is shown in Figure 12. The

calculated LTC2461/LTC2463 input signal attenuation vs

frequency at low frequencies is shown in Figure 13. The

converter noise level is about 2.2μVRMS and can be mod-

eled by a white noise source connected at the input of a

noise-free converter.

On a related note, the LTC2463 uses two separate A/D

converters to digitize the positive and negative inputs.

Each of these A/D converters has 2.2μVRMS transition

noise. If one of the input voltages is within this small

transition noise band, then the output will ﬂuctuate one

bit, regardless of the value of the other input voltage. If

both of the input voltages are within their transition noise

bands, the output can ﬂuctuate 2 bits.

For a simple system noise analysis, the VIN drive circuit can

be modeled as a single-pole equivalent circuit character-

ized by a pole location fi and a noise spectral density ni.

If the converter has an unlimited bandwidth, or at least a

bandwidth substantially larger than fi, then the total noise

contribution of the external drive circuit would be:

n = ni

π /2• f

Then, the total system noise level can be estimated as

the square root of the sum of (Vn2) and the square of the

LTC2461/LTC2463 noise ﬂoor (~2.2μV2).

LTC2463CDDPBF bảng dữ liệu(PDF) 16 Page - Linear Technology

LTC2463CDDPBF bảng dữ liệu(HTML) 16 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

bảng dữ liệu tải về

Link URL