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Data Output

by Transmitter

SCL From

Master

Start

Condition

S

1

2

8

9

Data Output

by Receiver

Clock Pulse for ACK

NACK

ACK

A

A

S

1

1

1

0

A2 A1

A0

0

Start Condition

SDA

R/W

ACK From Slave

ACK From Slave

P

B0

B1

B2

B3

X

X

X

X

Stop Condition

Slave Address

Control Register

A

NA

S

1

1

1

0

A2 A1

A0

1

SDA

P

B3 B2

B1 B0

Start Condition

R/W

ACK From Slave

NACK From Master

Stop Condition

Slave Address

Control Register

0

0

0

0

PCA9546A

WITH RESET FUNCTION

SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008

When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master

must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The

device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable

low during the high pulse of the ACK-related clock period (see Figure 7). Setup and hold times must be taken

into account.

Data is transmitted to the PCA9546A control register using the write mode shown in Figure 8.

Figure 8. Write Control Register

Data is read from the PCA9546A control register using the read mode shown in Figure 9.

Figure 9. Read Control Register

Copyright © 2005–2008, Texas Instruments Incorporated

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