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I

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

SDA

SCL

Start Condition

S

Stop Condition

P

SCL

Master

Transmitter/

Receiver

Slave

Receiver

Slave

Transmitter/

Receiver

Master

Transmitter

Master

Transmitter/

Receiver

Multiplexer

Slave

SDA

PCA9546A

WITH RESET FUNCTION

SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008

data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup

resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not

busy.

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high

period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 4).

Figure 4. Bit Transfer

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the

clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is

defined as the stop condition (P) (see Figure 5).

Figure 5. Definition of Start and Stop Conditions

A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the

message is the master, and the devices that are controlled by the master are the slaves (see Figure 6).

Figure 6. System Configuration

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not

limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA

line before the receiver can send an ACK bit.

6

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