SPMCK16Z4MPV16 datasheet(190/500 Pages) FREESCALE

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ANALOG-TO-DIGITAL CONVERTER

M68HC16 Z SERIES

8-4

USER’S MANUAL

STOP is set during system reset, and must be cleared before the ADC can be used.

Because analog circuit bias currents are turned off during low-power stop mode, the

ADC requires recovery time after STOP is cleared.

Execution of the CPU16 LPSTOP command places the entire modular microcontroller

in low-power stop mode. Refer to 5.3.4 Low-Power Operation for more information.

8.5.2 Freeze Mode

When the CPU16 in the modular microcontroller enters background debug mode, the

FREEZE signal is asserted. The type of response is determined by the value of the

FRZ[1:0] field in the ADCMCR. Table 8-1 shows the different ADC responses to

FREEZE assertion.

When the ADC freezes, the ADC clock stops and all sequential activity ceases.

Contents of control and status registers remain valid while frozen. When the FREEZE

signal is negated, ADC activity resumes.

If the ADC freezes during a conversion, activity resumes with the next step in the con-

version sequence. However, capacitors in the analog conversion circuitry discharge

while the ADC is frozen; as a result, the conversion will be inaccurate.

Refer to 4.14.4 Background Debug Mode for more information.

8.6 Analog Subsystem

The analog subsystem consists of a multiplexer, sample capacitors, a buffer amplifier,

an RC DAC array, and a high-gain comparator. Comparator output sequences the

successive approximation register (SAR). The interface between the comparator and

the SAR is the boundary between ADC analog and digital subsystems.

8.6.1 Multiplexer

The multiplexer selects one of 16 sources for conversion. Eight sources are internal

and eight are external. Multiplexer operation is controlled by channel selection field

CD:CA in register ADCTL1. Table 8-2 shows the different multiplexer channel

sources. The multiplexer contains positive and negative stress protection circuitry.

This circuitry prevents voltages on other input channels from affecting the current con-

version.

Table 8-1 FRZ Field Selection

FRZ[1:0]

Response

Ignore FREEZE, continue conversions

Reserved

Finish conversion in process, then freeze

Freeze immediately

Freescale Semiconductor, Inc.

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