SPMCK16Z4MPV16 datasheet(429/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-55

STOP — Low-Power Stop Mode Enable

0 = MCCI clock operates normally.

1 = MCCI clock is stopped.

When STOP is set, the MCCI enters low-power stop mode. The system clock input to

the module is disabled. While STOP is set, only MMCR reads and writes are guaran-

teed to be valid. Only writes to other MCCI registers are guaranteed valid. The SCI re-

ceiver and transmitter must be disabled before STOP is set. To stop the SPI, set the

HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP.

Bits [14:8] — Not Implemented

SUPV — Supervisor/Unrestricted

This bit has no effect because the CPU16 in the MCU operates only in supervisor

mode.

Bits [6:4] — Not Implemented

IARB[3:0] — Interrupt Arbitration ID

The IARB field is used to arbitrate between simultaneous interrupt requests of the

same priority. Each module that can generate interrupt requests must be assigned a

unique, non-zero IARB field value.

D.7.2 MCCI Test Register

MTEST — MCCI Test Register

$YFFC02

Used for factory test only.

D.7.3 SCI Interrupt Level Register/MCCI Interrupt Vector Register

Bits [15:14] — Not Implemented

ILSCIA[2:0], ILSCIB[2:0] — Interrupt Level for SCIA, SCIB

The values of ILSCIA[2:0] and ILSCIB[2:0] in ILSCI determine the interrupt request

levels of SCIA and SCIB interrupts, respectively. Program this field to a value from $0

(interrupts disabled) through $7 (highest priority).

ILSCI — SCI Interrupt Level Register

$YFFC04

NOT USED

ILSCIB[2:0]

ILSCIA[2:0]

MIVR

RESET:

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