SPMCK16Z4MPV16 datasheet(419/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-45

D.6.9 Port QS Pin Assignment Register/Data Direction Register

Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O. Set-

ting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI.

Table D-33 displays PQSPAR pin assignments.

DDRQS determines whether pins configured for general-purpose I/O are inputs or out-

puts. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin

an output. DDRQS affects both QSPI function and I/O function.Table D-34 shows the

effect of DDRQS on QSM pin function.

PQSPAR — PORT QS Pin Assignment Register

$YFFC16

DDRQS — PORT QS Data Direction Register

$YFFC17

NOT

USED

PQSPA6 PQSPA5 PQSPA4 PQSPA3

NOT

USED

PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0

RESET:

Table D-33 PQSPAR Pin Assignments

PQSPAR Field

PQSPAR Bit

Pin Function

PQSPA0

PQS0

MISO

PQSPA1

PQS1

MOSI

—

PQS21

SCK

NOTES:

1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE set in

SPCR1), in which case it becomes the QSPI serial clock SCK.

PQSPA3

PQS3

PCS0/SS

PQSPA4

PQS4

PCS1

PQSPA5

PQS5

PCS2

PQSPA6

PQS6

PCS3

—

PQS72

TXD

2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE set

in SCCR1), in which case it becomes the SCI serial output TXD.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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