SPMCK16Z4MPV16 datasheet(404/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-30

USER’S MANUAL

D.5.1 ADC Module Configuration Register

ADCMCR controls ADC operation during low-power stop mode, background debug

mode, and freeze mode.

STOP — Low-Power Stop Mode Enable

0 = Normal operation

1 = Low-power operation

STOP places the ADC in low-power state. Setting STOP aborts any conversion in

progress. STOP is set to logic level one during reset, and may be cleared to logic level

zero by the CPU16. Clearing STOP enables normal ADC operation. However, be-

cause analog circuitry bias current has been turned off, there is a period of recovery

before output stabilization.

FRZ[1:0] — Freeze Assertion Response

The FRZ field determines ADC response to assertion of the FREEZE signal when the

device is placed in background debug mode. Refer to Table D-25.

SUPV — Supervisor/Unrestricted

This bit has no effect because the CPU16 always operates in supervisor mode.

D.5.2 ADC Test Register

ADCTEST — ADC Test Register

$YFF702

Used for factory test only.

D.5.3 Port ADA Data Register

Port ADA is an input port that shares pins with the A/D converter inputs.

ADCMCR — ADC Module Configuration Register

$YFF700

STOP

FRZ

NOT USED

SUPV

NOT USED

RESET:

Table D-25 Freeze Encoding

FRZ[1:0]

Response

Ignore FREEZE, continue conversions

Reserved

Finish conversion in process, then freeze

Freeze immediately

PORTADA — Port ADA Data Register

$YFF706

NOT USED

PADA7

PADA6

PADA5

PADA4

PADA3

PADA2

PADA1

PADA0

RESET:

REFLECTS STATE OF THE INPUT PINS

Freescale Semiconductor, Inc.

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