TAS5616PHD datasheet(6/33 Pages) TI

6 / 33 page

2-CHANNEL

H-BRIDGE

BTL MODE

Output

H-Bridge 2

Hardwire

Over-

Current

Limit

PVDD

PowerSupply

Decoupling

GVDD, VDD,

& VREG

PowerSupply

Decoupling

SYSTEM

Power

Supplies

PVDD

GVDD (12V)/VDD (12V)

GND

50V

12V

GND

VAC

Bootstrap

Caps

BST_C

BST_D

nd Order

L-COutput

Filterfor

each

H-Bridge

OUT_C

OUT_D

Bootstrap

Caps

BST_A

BST_B

INPUT_A

nd Order

L-COutput

Filterfor

each

H-Bridge

OUT_A

OUT_B

Output

H-Bridge 1

Input

H-Bridge 1

INPUT_B

Hardwire

Mode

Control

Input

H-Bridge 2

INPUT_C

INPUT_D

Caps for

External

Filtering

Startup/Stop

System

microcontroller

PWM_A

PWM_B

PWM_C

PWM_D

(2)

TAS5518/

TAS5508/

TAS5086

I2C

Left-

Channel

Output

Right-

Channel

Output

VALID

/RESET

/AMP RESET

*NOTE1

*NOTE1: Logic ANDinoroutsidemicrocontroller

TAS5616

SLAS596B – JUNE 2009 – REVISED JANUARY 2010

www.ti.com

TERMINAL FUNCTIONS (continued)

TERMINAL

FUNCTION(1)

DESCRIPTION

PHD

DKD

NAME

NO.

Power supply for digital voltage regulator requires a 10-mF capacitor in parallel with a 0.1-mF

VDD

capacitor to GND for decoupling.

VI_CM

Analog comparator reference input requires close decoupling of 4.7 mF to AGND

VREG

Digital regulator supply filter pin requires 0.1-mF capacitor to AGND

TYPICAL SYSTEM BLOCK DIAGRAM

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