BQ76PL536PAPR datasheet(3/58 Pages) TI

3 / 58 page

bq76PL536

www.ti.com

SLUSA08A – DECEMBER 2009 – REVISED JULY 2010

TYPE(1)

DESCRIPTION

NO.

NAME

VC3

Sense voltage input terminal for the positive terminal of the third cell

CB3

Cell-balance control output

VC2

Sense voltage input terminal for the positive terminal of the second cell

CB2

Cell-balance control output

VC1

Sense voltage input terminal for positive terminal of the first cell

CB1

Cell-balance control output

VC0

Sense-voltage input terminal for negative terminal of first cell (VSS)

VSS1

VSS

AGND

Internal analog VREF (–)

VREF

Internal analog voltage reference (+), requires 10-µF, low-ESR ceramic capacitor to AGND for stability

LDOA

Internal analog 5-V LDO bypass connection, requires 2.2-µF ceramic capacitor for stability

LDOD1

Internal digital 5-V LDO bypass connection 1, requires 2.2-µF ceramic capacitor for stability. This pin is tied

internally to LDOD2. This pin should be tied to LDOD2 externally.

TS1–

Differential temperature sensor input

TS1+

Differential temperature sensor input

CONV_S

Input from the adjacent lower bq76PL536 to initiate a conversion

DRDY_S

Current-mode output indicating conversion data is ready to the next lower bq76PL536

ALERT_S

Current-mode output indicating a system status change to the next lower bq76PL536

FAULT_S

Current-mode output

VSS2

VSS

SCLK_S

Current-mode input SPI clock from the next-lower bq76PL536

SDO_S

Current-mode output for SPI data to the next-lower bq76PL536

SDI_S

Current-mode input for SPI data from the next-lower bq76PL536

CS_S

Current-mode input SPI chip-select (slave-select) from the next-lower bq76PL536

–

No connection

AUX

Switched 1-mA limited output from REG50

REG50

5-V user LDO output, requires 2.2-µF ceramic capacitor for stability

VSS3

VSS

VSS4

VSS

VSS5

VSS

CONV_H

Host-to-device interface – initiates a synchronous conversion. Pin has 250-nA internal sink to VSS.

DRDY_H

Host-to-device interface – conversion complete, data-ready indication

ALERT_H

Host-to-device interface – ALERT condition detected in this or higher (North) device

FAULT_H

Host-to-device interface – FAULT condition detected in this or higher (North) device

SCLK_H

Host-to-device interface – SPI clock from host

SDO_H

Host-to-device interface – data from device to host (host MISO signal), 3-state pin, 250-nA internal pullup

SDI_H

Host-to-device interface – data from host to device (host MOSI signal)

CS_H

Host-to-device interface – active-low chip select from host. Internal 100-k

Ω pullup resistor

HSEL

Host interface enable, 0 = enable, 1 = disable

GPIO

IOD

Digital open-drain I/O. A 10 k

Ω–2-MΩ pullup is recommended.

LDOD2

Internal digital 5-V LDO bypass connection 2, requires 2.2-µF ceramic capacitor for stability. This pin is tied

internally to LDOD1. This pin should be tied to LDOD1 externally.

GPAI–

General-purpose (differential) analog input, connect to VSS if unused.

GPAI+

General-purpose (differential) analog input, connect to VSS if unused.

VSS6

VSS

TEST

Factory Test pin. Connect to VSS in user circuitry. This pin includes ~100K internal pull-down

–

No connect

CS_N

Current-mode output used to select the next-higher bq76PL536 for SPI communication

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