BQ76PL536PAPR datasheet(28/58 Pages) TI

28 / 58 page

DEV ADDR

1 byte

time

REG ADDR

CNT = n

0x00

READn...

CRC

n + 1 placeholderbytes

SDI

SDO

0x00

StartReg Address

Device Address

ReadLengthn

ReadData 1

R/W

ReadDatan

CRC

ReadPacket

CS Assertion

DEV ADDR

1 byte

time

REG ADDR

WRT DATA

CRC

DEV ADDR

REG ADDR

Startofnextpacket

SDI

...

Reg Address

Device Address

RegData

CRC

R/W

WritePacket

CS Assertion

bq76PL536

SLUSA08A – DECEMBER 2009 – REVISED JULY 2010

www.ti.com

Figure 8. READ Packet Format

Figure 9. READ Packet Detail

Data Write Packet

When the bq76PL536 is selected (CS_S is active and the bq76PL536 has been addressed) and a write request

has been initiated, the bq76PL536 receives data through the SDI_S pin, which is connected to the SDO_N of the

lower device. For the first device in the stack, the data is input to the SDI_H pin from the host, and transmitted up

the stack on the SDI_S pin to the SDI_N pin of the next higher device. If enabled, the device checks the CRC,

which it expects as the last byte sent. If the CRC is valid, no action is taken. If the CRC is invalid or missing, the

device asserts the ALERT_S signal to the next lower device, which ripples down the stack to the ALERT_H pin

on the lowest device. The host should then take action to clear the condition.

Unused or undefined register bits should be written as zeros.

Figure 10. WRITE Packet Format

Figure 11. WRITE Packet Detail

Submit Documentation Feedback

Product Folder Link(s) :bq76PL536

BQ76PL536PAPR bảng dữ liệu(PDF) 28 Page - Texas Instruments

BQ76PL536PAPR bảng dữ liệu(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

bảng dữ liệu tải về

Link URL