PC912XDP512F0CFVR datasheet(370/1348 Pages) FREESCALE

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

370

Freescale Semiconductor

8.3.2.2

PWM Polarity Register (PWMPOL)

The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the

PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle

and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts

low and then goes high when the duty count is reached.

Read: Anytime

Write: Anytime

NOTE

PPOLx register bits can be written anytime. If the polarity is changed while

a PWM signal is being generated, a truncated or stretched pulse can occur

during the transition

8.3.2.3

PWM Clock Select Register (PWMCLK)

Each PWM channel has a choice of two clocks to use as the clock source for that channel as described

below.

Read: Anytime

Write: Anytime

76543210

PPOL7

PPOL6

PPOL5

PPOL4

PPOL3

PPOL2

PPOL1

PPOL0

Reset

00000000

Figure 8-4. PWM Polarity Register (PWMPOL)

Table 8-2. PWMPOL Field Descriptions

Field

Description

7–0

PPOL[7:0]

Pulse Width Channel 7–0 Polarity Bits

0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is

reached.

1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is

reached.

76543210

PCLK7

PCLKL6

PCLK5

PCLK4

PCLK3

PCLK2

PCLK1

PCLK0

Reset

00000000

Figure 8-5. PWM Clock Select Register (PWMCLK)

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