PC912XDP512F0CFVR datasheet(82/1348 Pages) FREESCALE

82 / 1348 page

Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

2.2

External Signal Description

This section lists and describes the signals that connect off chip.

2.2.1

VDDPLL and VSSPLL — Operating and Ground Voltage Pins

These pins provide operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows

the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, VDDPLL

and VSSPLL must be connected to properly.

2.2.2

XFC — External Loop Filter Pin

A passive external loop ﬁlter must be placed on the XFC pin. The ﬁlter is a second-order, low-pass ﬁlter

that eliminates the VCO input ripple. The value of the external ﬁlter network and the reference frequency

determines the speed of the corrections and the stability of the PLL. Refer to the device speciﬁcation for

calculation of PLL Loop Filter (XFC) components. If PLL usage is not required, the XFC pin must be tied

to VDDPLL.

Figure 2-2. PLL Loop Filter Connections

2.2.3

RESET — Reset Pin

RESET is an active low bidirectional reset pin. As an input. it initializes the MCU asynchronously to a

known start-up state. As an open-drain output, it indicates that a system reset (internal to the MCU) has

been triggered.

2.3

Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the CRG.

MCU

XFC

VDDPLL

PC912XDP512F0CFVR bảng dữ liệu(PDF) 82 Page - Freescale Semiconductor, Inc