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DSM2180F3 bảng dữ liệu(PDF) 50 Page - STMicroelectronics

tên linh kiện DSM2180F3
Giải thích chi tiết về linh kiện  DSM (Digital Signal Processor System Memory) for analog devices ADSP-218X family (5 V supply)
PDF  63 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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DSM2180F3 bảng dữ liệu(HTML) 50 Page - STMicroelectronics

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Table 28. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0.
2. CLKIN (PD1) tCLCL = tCH + tCL .
Table 29. CPLD Macrocell Asynchronous Clock Mode Timing
Symbol
Parameter
Conditions
-90
Fast PT
Aloc
Turbo
Off
Slew
Rate1
Unit
Min
Max
fMAX
Maximum Frequency
External Feedback
1/(tS+tCO)
30.30
MHz
Maximum Frequency
Internal Feedback
(fCNT)
1/(tS+tCO–10)
43.48
MHz
Maximum Frequency
Pipelined Data
1/(tCH+tCL)
50.00
MHz
tS
Input Setup Time
15
Add 2
Add 10
ns
tH
Input Hold Time
0
ns
tCH
Clock High Time
Clock Input
10
ns
tCL
Clock Low Time
Clock Input
10
ns
tCO
Clock to Output Delay
Clock Input
18
Sub 2
ns
tARD
CPLD Array Delay
Any Macrocell
16
Add 2
ns
tMIN
Minimum Clock Period 2
tCH+tCL
20
ns
Symbol
Parameter
Conditions
-90
PT
Aloc
Turbo
Off
Slew
Rate
Unit
Min
Max
fMAXA
Maximum Frequency
External Feedback
1/(tSA+tCOA)
26.32
MHz
Maximum Frequency
Internal Feedback
(fCNTA)
1/(tSA+tCOA–10)
35.71
MHz
Maximum Frequency
Pipelined Data
1/(tCHA+tCLA)
41.67
MHz
tSA
Input Setup Time
8
Add 2
Add 10
ns
tHA
Input Hold Time
12
ns
tCHA
Clock Input High Time
12
Add 10
ns
tCLA
Clock Input Low Time
12
Add 10
ns
tCOA
Clock to Output Delay
30
Add 10
Sub 2
ns
tARDA
CPLD Array Delay
Any Macrocell
16
Add 2
ns
tMINA
Minimum Clock Period
1/fCNTA
28
ns



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