TSA1002IFT datasheet(17/20 Pages) STMICROELECTRONICS

17 / 20 page

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Product(s)

- Obsolete

Product(s)

TSA1002

17/20

Clock input

The quality of your converter is very dependant on

your clock input accuracy, in terms of aperture

jitter; the use of low jitter crystal controlled

oscillator is recommended.

The clock power supplies must be separated from

the ADC output ones to avoid digital noise

modulation at the output.

It is recommended to keep the circuit clocked, to

avoid random states, before applying the supply

voltages.

Layout precautions

To use the ADC circuits in the best manner at high

frequencies, some precautions have to be taken

for power supplies:

- First of all, the implementation of 4 separate

proper supplies and ground planes (analog,

digital, internal and external buffer ones) on the

PCB is recommended for high speed circuit

applications to provide low inductance and low

resistance common return.

The separation of the analog signal from the

digital part is essential to prevent noise from

coupling onto the input signal.

- Power supply bypass capacitors must be placed

as close as possible to the IC pins in order to

improve high frequency bypassing and reduce

harmonic distortion.

- Proper termination of all inputs and outputs is

needed; with output termination resistors, the

amplifier load will be only resistive and the stability

of the amplifier will be improved. All leads must be

wide and as short as possible especially for the

analog input in order to decrease parasitic

capacitance and inductance.

- To keep the capacitive loading as low as

possible at digital outputs, short lead lengths of

routing are essential to minimize currents when

the output changes. To minimize this output

capacitance, buffers or latches close to the output

pins will relax this constraint.

- Choose component sizes as small as possible

(SMD).

EVAL1002 evaluation board

The characterization of the board has been made

with a fully ADC devoted test bench as shown on

Figure 11. The analog signal must be filtered to be

very pure.

The dataready signal is the acquisition clock of the

logic analyzer.

The ADC digital outputs are latched by the

74LCX573 octal buffers.

All characterization measurement has been made

with an input amplitude of +0.2dB for static

parameters and -0.5dB for dynamic parameters.

Figure 11 : Analog to Digital Converter characterization bench

Sine Wave

Generator

HP8644

ADC

evaluation

board

Pulse

Generator

Logic

Analyzer

Sine Wave

Generator

HP8644

HP8133

Vin

Clk

Data

Clk

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