STA015 datasheet(41/56 Pages) STMICROELECTRONICS

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STA015

GPSO_ENABLE

Address: 0xB9 (185)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

This register enable/disable the GPSO interface.

Setting the GEN bit will enable the serial interface for ADPCM data retrieving. Reset GEN bit to disable

GPSO interface.

GPSO_CONF

Address: 0xBA (186)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

GSP: GPSO clock polarity sing this bit the GPSO_SCKR polarity can be controlled. Clearing GSP bit data

on GPSO_DATA line will be provided on the rising edge of GPSO_SCKR (sampling on falling

edge). Setting GSP bit data are provided on falling edge of GPSO_SCKR (sampling on rising edge)

GRP: GPSO Request Polarity This bit is used to determine the polarity of GPSO_REQ signal. If GRP bit

is cleared data are valid on GPSO_REQ signal high. If this bit is set data are valid on GPSO_REQ

signal low

ADC_ENABLE

Address: 0xBB (187)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

This register controls if the ADPCM data to be encoded comes from A/D interface or from MP3 bitstream

input interface.

If ADCEN bit is set data to be encoded comes from ADC interface, otherwise data comes from MP3

stream interface

MSB

LSB

XXXX

GEN

MSB

LSB

XXXX

GRP

GSP

MSB

LSB

XXXX

ADCEN

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