DSP56303 datasheet(46/108 Pages) FREESCALE

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DSP56303 Technical Data, Rev. 11

2-26

Freescale Semiconductor

Specifications

2.5.5.4 Arbitration Timings

Table 2-14.

Arbitration Bus Timings1

No.

Characteristics

Expression2

100 MHz

Unit

Min

Max

212

CLKOUT high to BR assertion/deassertion3

0.0

4.0

213

BG asserted/deasserted to CLKOUT high (setup)

4.0

—

214

CLKOUT high to BG deasserted/asserted (hold)

0.0

—

215

BB deassertion to CLKOUT high (input set-up)

4.0

—

216

CLKOUT high to BB assertion (input hold)

0.0

—

217

CLKOUT high to BB assertion (output)

0.0

4.0

218

CLKOUT high to BB deassertion (output)

0.0

4.0

219

BB high to BB high impedance (output)

—

4.5

220

CLKOUT high to address and controls active

0.25

× TC

2.5

—

221

CLKOUT high to address and controls high impedance

0.75

× T

—7.5

222

CLKOUT high to AA active

0.25

× TC

2.5

—

223

CLKOUT high to AA deassertion

maximum: 0.25

× TC + 4.0

2.0

6.5

224

CLKOUT high to AA high impedance

0.75

× T

—7.5

Notes:

Synchronous bus arbitration is not recommended. Use Asynchronous mode whenever possible.

An expression is used to compute the maximum or minimum value listed, as appropriate. For timing 223, the minimum is an

absolute value.

T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is deasserted for internal

accesses and asserted for external accesses.

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