DSP56303 datasheet(33/108 Pages) FREESCALE

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AC Electrical Characteristics

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-13

111

WR deassertion to data high impedance

—

0.25

× TC + 0.2

≤WS ≤3]

1.25

× TC + 0.2

≤WS ≤7]

2.25

× TC + 0.2

[WS > 8]

—

2.7

12.7

22.7

112

Previous RD deassertion to data active (write)

—

1.25

× TC – 4.0

≤WS ≤3]

2.25

× TC – 4.0

≤WS ≤7]

3.25

× T

C – 4.0

[WS > 8]

8.5

18.5

28.5

—

113

RD deassertion time

—

0.75

× T

C −4.0

≤WS ≤3]

1.75

× TC −4.0

≤WS ≤7]

2.75

× TC −4.0

[WS

≥ 8]

3.5

13.5

23.5

—

114

WR deassertion time

—

0.5

× TC −4.0

[WS = 1]

TC −4.0

≤WS ≤3]

2.5

× TC −4.0

≤WS ≤7]

3.5

× TC −4.0

[WS

≥ 8]

1.0

6.0

21.0

31.0

—

115

Address valid to RD assertion

—

0.5

× TC −4.0

1.0

—

116

RD assertion pulse width

—

(WS + 0.25)

× T

C −4.0

8.5

—

117

RD deassertion to address not valid

—

0.25

× TC −2.0

≤WS ≤3]

1.25

× TC −2.0

≤WS ≤7]

2.25

× T

C −2.0

[WS

≥ 8]

0.5

10.5

20.5

—

118

TA setup before RD or WR deassertion4

—0.25

× T

C + 2.0

4.5

—

119

TA hold after RD or WR deassertion

—

Notes:

WS is the number of wait states specified in the BCR. An expression is used to compute the number listed as the minimum or

maximum value, as appropriate.

Timings 100, 107 are guaranteed by design, not tested.

All timings for 100 MHz are measured from 0.5

× Vcc to 0.5 × Vcc.

Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted.

VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100°C, CL = 50 pF

Table 2-8.

SRAM Read and Write Accesses (Continued)

No.

Characteristics

Symbol

Expression1

100 MHz

Unit

Min

Max

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