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Register Descriptions

Power-On Reset

Reset Input (RESET)

TCA6408

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007

The input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is

defined as an input or an output by the configuration register. They act only on read operation. Writes to this

register have no effect. The default value (X) is determined by the externally applied logic level. Before a read

register will be accessed next.

Register 0 (Input Port Register)

BIT

I-7

I-6

I-5

I-4

I-3

I-2

I-1

I-0

DEFAULT

X

X

X

X

X

X

X

X

The output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this

register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.

Register 1 (Output Port Register)

BIT

O-7

O-6

O-5

O-4

O-3

O-2

O-1

O-0

DEFAULT

1

1

1

1

1

1

1

1

The polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configuration

register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in

this register is cleared (written with a 0), the corresponding port pin's original polarity is retained.

Register 2 (Polarity Inversion Register)

BIT

N-7

N-6

N-5

N-4

N-3

N-2

N-1

N-0

DEFAULT

0

0

0

0

0

0

0

0

The configuration register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1,

the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is

cleared to 0, the corresponding port pin is enabled as an output.

Register 3 (Configuration Register)

BIT

C-7

C-6

C-5

C-4

C-3

C-2

C-1

C-0

DEFAULT

1

1

1

1

1

1

1

1

back up to the operating voltage for a power-reset cycle.

state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels

active connection is used.

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