LTC3589 datasheet(33/44 Pages) LINER

33 / 44 page

LTC3589

3589p

Figure 19. LTC3589 I2C Serial Port Multiple Write Pattern

34567

0 WR

S7 S6 S5S4S3S2S1 S0

D7 D6 D5 D4 D3 D2 D1 D0

S7 S6 S5S4S3S2S1 S0

D7 D6 D5 D4 D3 D2 D1 D0

34567

4567

34567

SCL

ADDRESS

SUB-ADDRESS

DATA

SUB-ADDRESS

DATA

3589 F19

ACK

START

SDA

STOP

Figure 18. LTC3589 I2C Timing

tSU, DAT

tHD, STA

tHD, DAT

SDA

SCL

tHD, STA

tSU, STO

3589 F18

tBUF

tLOW

tHIGH

START

CONDITION

REPEATED START

CONDITION

STOP

START

tSP

OPERATION

I2C Bus Speed

The I2C port operates at speeds up to 400kHz. It has

built-in timing delays to ensure correct operation when

addressed from an I2C compliant master device. It also

contains input ﬁlters designed to suppress glitches should

the bus become corrupted.

I2C START and STOP Conditions

A bus master signals the beginning of communications

by transmitting a START condition. A START condition is

generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave

write or the slave read address. Once data is written to the

LTC3589, the master may transmit a STOP condition that

commands the LTC3589 to act upon its new command set.

A STOP condition is sent by the master by transitioning

SDA from LOW to HIGH while SCL is HIGH. The bus it then

free for communication with another I2C device.

I2C Byte Format

Each byte sent to or received from the LTC3589 must

be 8 bits long followed by an extra clock cycle for the

acknowledge bit. The data should be sent to the LTC3589

most signiﬁcant bit (MSB) ﬁrst.

I2C Acknowledge

The acknowledge signal is used for handshaking between

the master and the slave. When the LTC3589 is written

to (write address), it acknowledges its write address and

subsequent register address and data bytes. When read-

ing from the LTC3589, it acknowledges its read address

and 8-bit status byte.

An acknowledge pulse (active LOW) generated by the

LTC3589 lets the master know that the latest byte of informa-

tion was transferred. The master generates the clock cycle

and releases the SDA line (HIGH) during the acknowledge

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