LTC3589 datasheet(32/44 Pages) LINER

32 / 44 page

LTC3589

3589p

OPERATION

Figure 17. IRQ and IRQSTAT Status Register Fault Timing

IRQ

IRQSTAT

CLIRQ

3589 F17

TSD, UV,

OR PGOOD FAULT

1 SEC

Figure 16. IRQ and IRQSTAT Status Register Warning Timing

IRQ

IRQSTAT

CLIRQ

3589 F16

TSD OR UV

WARNING

Figure 16 shows the timing of the IRQ and IRQSTAT

status register following a warning (VIN <2.9V or high

temperature warning) event. When a warning occurs, IRQ

is latched LOW and bit IRQSTAT[4] or IRQSTAT[5] is set.

IRQ remains LOW until I2C command register CLIRQ is

written. The status bits in the IRQSTAT register will remain

active until CLIRQ is accessed and the warning condition

has passed.

Figure 17 shows the timing of the IRQ pin and IRQSTAT

status register following a fault induced hard shutdown

event. When a fault occurs, IRQ is latched LOW and bit

IRQSTAT[3], IRQSTAT[5], or IRQSTAT[7] is set. IRQ re-

mains LOW until I2C command register CLIRQ is accessed.

When the CLIRQ command has been issued, the IRQSTAT

status bit remains set for the one second enable inhibit

time or as long as the fault condition persists, whichever

is longer.

Fault Induced Shutdown

Any of the three fault conditions will initiate a hard reset

shutdown triggering the following events: 1) A bit corre-

sponding to the fault is set in status register IRQSTAT, 2)

IRQ and WAKE pins are pulled LOW, 3) enable pin inputs

are ignored and the regulators are disabled, 4) all enable

bits and software control mode bit in the output voltage

enable OVEN command register are cleared, and 5) the

pushbutton controller is sent to the PDN state for one

second and then to POFF. Re-enabling of regulators is

inhibited until both the fault condition and the one second

time out have passed to allow regulator outputs sufﬁcient

time to discharge. When one second timeout and the fault

condition are both passed, if PWR_ON is HIGH, WAKE will

come up and the LTC3589 will respond to any enable pins

that are also HIGH.

I2C OPERATION

I2C Interface

The LTC3589 communicates with a bus master using the

standard I2C 2-wire interface. The two bus lines, SDA and

SCL, must be HIGH when the bus is not in use. External

pull-up resistors or current sources, such as the LTC1694

SMBus accelerator, are required on these lines. The

LTC3589 is both a slave receiver and slave transmitter. The

I2C control signals, SDA and SCL are scaled internally to

the DVDD supply. DVDD should be connected to the same

power supply as the bus pull-up resistors.

The I2C port has an under voltage lockout on the DVDD

pin. When DVDD is below approximately 1V, the I2C serial

port is reset to power-on states and registers are set to

default values.

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