ADS5281IPFPR datasheet(12/44 Pages) TI

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D9 D10 D11 D0

D5 D6

D9 D10 D11

D4 D5

D9 D10 D11

Sample n

Sample n+12

PROP

t (A)

12clockslatency

AnalogInput

ClockInput

6XADCLK

LCLK

1XADCLK

ADCLK

SERIAL DATA

OUT

SAMPLE

Sample n+13

SU1

SU2

LCLK

OUT

TIMING CHARACTERISTICS

(1) (2)

ADS5281

ADS5282

SBAS397H – DECEMBER 2006 – REVISED MARCH 2008

LVDS TIMING DIAGRAM

DEFINITION OF SETUP AND HOLD TIMES

tSU = min(tSU1, tSU2)

tH = min(tH1, tH2)

ADS528x

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

1.5

4.5

Aperture delay variation

Channel-to-channel within the same device (3

σ)

±20

Aperture jitter

400

Time to valid data after coming out of

µs

COMPLETE POWER-DOWN mode

Time to valid data after coming out of PARTIAL

tWAKE

Wake-up time

POWER-DOWN mode (with clock continuing to

µs

run during power-down)

Time to valid data after stopping and restarting

µs

the input clock

Clock

Data latency

cycles

(1)

Timing characteristics are common to the ADS528x family.

(2)

Timing parameters are ensured by design and characterization; not production tested.

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