Block Guide — S12BDM V4

15

3.2 BDM CCR Holding Register

Figure 3-2 BDM CCR Holding Register (BDMCCR)

Read: All modes

Write: All modes

NOTE:

When BDM is made active, the CPU stores the value of the CCR register in the

BDMCCR register. However, out of special single-chip reset, the BDMCCR is set

to $D8 and not $D0 which is the reset value of the CCR register.

When entering background debug mode, the BDM CCR holding register is used to save the contents of

the condition code register of the user’s program. It is also used for temporary storage in the standard BDM

firmware mode. The BDM CCR holding register can be written to modify the CCR value.

3.3 BDM Internal Register Position Register

Figure 3-3 BDM Internal Register Position (BDMINR)

Read: All modes

Write: Never

REG14–REG11 — Internal register map position

These four bits show the state of the upper five bits of the base address for the system’s relocatable

register block. BDMINR is a shadow of the INITRG register which maps the register block to any

2K byte space within the first 32K bytes of the 64K byte address space.

Register address $FF06

7

6

5

4

3

2

1

0

R

CCR7

CCR6

CCR5

CCR4

CCR3

CCR2

CCR1

CCR0

W

Reset:

0

0

0

0

0

0

0

0

Register address $FF07

7

6

5

4

3

2

1

0

R

0

REG14

REG13

REG12

REG11

0

0

0

W

Reset:

0

0

0

0

0

0

0

0

= Unimplemented or Reserved