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PIC16F722-E/ML bảng dữ liệu(PDF) 185 Page - Microchip Technology

tên linh kiện PIC16F722-E/ML
Giải thích chi tiết về linh kiện  28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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PIC16F722-E/ML bảng dữ liệu(HTML) 185 Page - Microchip Technology

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© 2009 Microchip Technology Inc.
DS41341E-page 185
PIC16F72X/PIC16LF72X
17.2.10
CLOCK SYNCHRONIZATION
When the CKP bit is cleared, the SCL output is held low
once it is sampled low. therefore, the CKP bit will not
stretch the SCL line until an external I2C master device
has already asserted the SCL line low. The SCL output
will remain low until the CKP bit is set and all other
devices on the I2C bus have released SCL. This
ensures that a write to the CKP bit will not violate the
minimum
high
time
requirement
for
SCL
(Figure 17-14).
17.2.11
SLEEP OPERATION
While in Sleep mode, the I2C module can receive
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
FIGURE 17-14:
CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX-1
DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock



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