PIC16F722-ESLASHML datasheet(33/302 Pages) MICROCHIP

33 / 302 page

DS41341E-page 33

PIC16F72X/PIC16LF72X

3.0

RESETS

The PIC16F72X/PIC16LF72X differentiates between

various kinds of Reset:

Power-on Reset (POR)

WDT Reset during normal operation

WDT Reset during Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

Brown-out Reset (BOR)

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset (POR)

•MCLR Reset

•MCLR Reset during Sleep

•WDT Reset

• Brown-out Reset (BOR)

Most registers are not affected by a WDT wake-up

since this is viewed as the resumption of normal

operation. TO and PD bits are set or cleared differently

in different Reset situations, as indicated in Table 3-3.

These bits are used in software to determine the nature

of the Reset.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 3-1.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 23.0 “Electrical

Specifications” for pulse width specifications.

FIGURE 3-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

MCLR/VPP

VDD

OSC1/

WDT

Module

POR

OST/PWRT

WDTOSC

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

11-bit Ripple Counter

Reset

Enable OST

Enable PWRT

Sleep

Brown-out(1)

Reset

BOREN

CLKIN

Note

Refer to the Configuration Word Register 1 (Register 8-1).

MCLRE

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