PIC12F1822-ISLASHMF datasheet(230/398 Pages) MICROCHIP

230 / 398 page

PIC12F/LF1822/16F/LF1823

DS41413A-page 230

Preliminary

 2010 Microchip Technology Inc.

24.2.2

SPI MODE OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSP1CON1<5:0> and SSP1STAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK1 is the clock output)

• Slave mode (SCK1 is the clock input)

• Clock Polarity (Idle state of SCK1)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK1)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

To enable the serial port, SSP1 Enable bit, SSP1EN of

the SSP1CON1 register must be set. To reset or recon-

figure SPI mode, clear the SSP1EN bit, re-initialize the

SSP1CONx registers and then set the SSP1EN bit.

This configures the SDI, SDO, SCK and SS pins as

serial port pins. For the pins to behave as the serial port

function, some must have their data direction bits (in

the TRIS register) appropriately programmed as

follows:

• SDI must have corresponding TRIS bit set

• SDO must have corresponding TRIS bit cleared

• SCK (Master mode) must have corresponding

TRIS bit cleared

• SCK (Slave mode) must have corresponding

TRIS bit set

•SS must have corresponding TRIS bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

The MSSP1 consists of a transmit/receive shift register

(SSP1SR) and a buffer register (SSP1BUF). The

SSP1SR shifts the data in and out of the device, MSb

first. The SSP1BUF holds the data that was written to

the SSP1SR until the received data is ready. Once the

8 bits of data have been received, that byte is moved to

the SSP1BUF register. Then, the Buffer Full Detect bit,

BF of the SSP1STAT register, and the interrupt flag bit,

SSP1IF, are set. This double-buffering of the received

data (SSP1BUF) allows the next byte to start reception

before reading the data that was just received. Any

write

the

SSP1BUF

during

transmission/reception of data will be ignored and the

write collision detect bit, WCOL, of the SSP1CON1

WCOL bit to allow the following write(s) to the

SSP1BUF register to complete successfully.

When the application software is expecting to receive

valid data, the SSP1BUF should be read before the

next byte of data to transfer is written to the SSP1BUF.

The Buffer Full bit, BF of the SSP1STAT register,

indicates when SSP1BUF has been loaded with the

received data (transmission is complete). When the

SSP1BUF is read, the BF bit is cleared. This data may

be irrelevant if the SPI is only a transmitter. Generally,

the MSSP1 interrupt is used to determine when the

transmission/reception has completed. If the interrupt

method is not going to be used, then software polling

can be done to ensure that a write collision does not

occur.

The SSP1SR is not directly readable or writable and

can only be accessed by addressing the SSP1BUF

the various Status conditions.

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