PIC12F1822-ISLASHMF datasheet(92/398 Pages) MICROCHIP

92 / 398 page

PIC12F/LF1822/16F/LF1823

DS41413A-page 92

Preliminary

 2010 Microchip Technology Inc.

8.5.4

PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as

shown in Register 8-4.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0

R-0/0

R/W-0/0

TMR1GIF

ADIF

RCIF

TXIF

SSP1IF

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 6

ADIF: A/D Converter Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 5

RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 4

TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 3

SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 2

CCP1IF: CCP1 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 1

TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 0

TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

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