PIC32MX320F032H datasheet(49/172 Pages) MICROCHIP

49 / 172 page

BF88_6060

LATB(4,5)

31:16

—

15:0

LATB<15:0>

BF88_6070 ODCB(4,5)

31:16

—

15:0

ODCB<15:0>

BF88_6080

TRISC

31:16

—

15:0

TRISC15

TRISC14

TRISC13

TRISC12

—

TRISC4(6) TRISC3(6) TRISC2(6) TRISC1(6)

—

BF88_6090

PORTC

31:16

—

15:0

RC15

RC14

RC13

RC12

—

RC4(6)

RC3(6)

RC2(6)

RC1(6)

—

BF88_60A0

LATC

31:16

—

15:0

LATC15

LATC14

LATC13

LATC12

—

—LATC4(6)

LATC3(6)

LATC2(6)

LATC1(6)

—

BF88_60B0

ODCC

31:16

—

15:0

ODCC15

ODCC14

ODCC13

ODCC12

—

ODCC4(6) ODCC3(6) ODCC2(6) ODCC1(6)

—

BF88_60C0

TRISD

31:16

—

15:0 TRISD15(6) TRISD14(6) TRISD13(6) TRISD12(6)

TRISD<11:8>

TRISD<7:0>

BF88_60D0

PORTD

31:16

—

15:0

RD15(6)

RD14(6)

RD13(6)

RD12(6)

RD<11:8>

RD<7:0>

BF88_60E0

LATD

31:16

—

15:0

LAT15(6)

LAT14(6)

LAT13(6)

LAT12(6)

LATD<11:8>

LATD<7:0>

BF88_60F0

ODCD

31:16

—

15:0 ODCD15(6) ODCD14(6) ODCD13(6) ODCD12(6)

ODCD<11:8>

ODCD<7:0>

BF88_6100

TRISE

31:16

—

15:0

—

TRISE9(6) TRISE8(6)

TRISE<7:0>

BF88_6110

PORTE

31:16

—

15:0

—

—RE9(6)

RE8(6)

RE<7:0>

BF88_6120

LATE

31:16

—

15:0

—

—LATE9(6)

LATE8(6)

LATE<7:0>

TABLE 4-17:

PORT A-G REGISTERS MAP(11) (CONTINUED)

SFR

Virtual

Addr

SFR

Name

Bits

31/15

Bits

30/14

Bits

29/13

Bits

28/12

Bits

27/11

Bits

26/10

Bits

25/9

Bits

24/8

Bits

23/7

Bits

22/6

Bits

21/5

Bits

20/4

Bits

19/3

Bits

18/2

Bits

17/1

Bits

16/0

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.

JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the

user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.

On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain

these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.

JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the

user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.

Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.

Not implemented on 64-pin devices. Read as ‘0’.

Not implemented on 64-pin USB devices. Read as ‘0’.

Not implemented on 100-pin USB devices. Read as ‘0’.

Not available as a general purpose I/O pin when USB module is enabled.

10:

Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.

11:

All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-

mation.

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