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39 / 172 page  BF80_3220 OC2RS 31:16 15:0 OC2RS<31:0> BF80_3400 OC3CON 31:16 — — — — — — — — — — — — — — — — 15:0 ON FRZ SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> BF80_3410 OC3R 31:16 OC3R<31:0> 15:0 BF80_3420 OC3RS 31:16 15:0 OC3RS<31:0> BF80_3600 OC4CON 31:16 — — — — — — — — — — — — — — — — 15:0 ON FRZ SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> BF80_3610 OC4R 31:16 OC4R<31:0> 15:0 BF80_3620 OC4RS 31:16 15:0 OC4RS<31:0> BF80_3800 OC5CON 31:16 — — — — — — — — — — — — — — — — 15:0 ON FRZ SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> BF80_3810 OC5R 31:16 OC5R<31:0> 15:0 BF80_3820 OC5RS 31:16 OC5RS<31:0> 15:0 TABLE 4-5: OUTPUT COMPARE 1-5 REGISTERS MAP(1) (CONTINUED) SFR Virtual Addr SFR Name Bits 31/15 Bits 30/14 Bits 29/13 Bits 28/12 Bits 27/11 Bits 26/10 Bits 25/9 Bits 24/8 Bits 23/7 Bits 22/6 Bits 21/5 Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 Bits 16/0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor- mation. TABLE 4-6: I2C1-2 REGISTERS MAP(1) SFR Virtual Addr SFR Name Bits 31/15 Bits 30/14 Bits 29/13 Bits 28/12 Bits 27/11 Bits 26/10 Bits 25/9 Bits 24/8 Bits 23/7 Bits 22/6 Bits 21/5 Bits 20/4 Bits 19/3 Bits 18/2 Bits 17/1 Bits 16/0 BF80_5000 I2C1CON 31:16 — — — — — — — — — — — — — — — — 15:0 ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN BF80_5010 I2C1STAT 31:16 — — — — — — — — — — — — — — — — 15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF BF80_5020 I2C1ADD 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — ADD<9:0> BF80_5030 I2C1MSK 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — MSK<9:0> BF80_5040 I2C1BRG 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — I2C1BRG<11:0> Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Regis- ters” for more information. |
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