PCF8566TS datasheet(34/48 Pages) NXP

34 / 48 page

PCF8566_7

Product data sheet

Rev. 07 — 25 February 2009

34 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8566s. This synchronization is guaranteed after the power-on reset. The only time

that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments or by deﬁning a multiplex mode when PCF8566s with

differing SA0 levels are cascaded).

SYNC is organized as an input/output pin; the output selection being realized as an

open-drain driver with an internal pull-up resistor. A PCF8566 asserts the SYNC line at

the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the ﬁrst PCF8566 to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCF8566 are shown in Figure 27.

Fig 26. Cascaded PCF8566 conﬁguration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

CLK

OSC

SYNC

17 to 40

13 to 16

512

910

24 segment drives

4 backplanes

24 segment drives

LCD PANEL

(up to 1536

elements)

PCF8566

SA0

mgg384

SDA

SCL

SYNC

CLK

OSC

512

17 to 40

BP0 to BP3

(open-circuit)

SA0

BP0 to BP3

VDD

VLCD

VSS

VDD

VLCD

VSS

VLCD

VDD

VSS

≤

trise

2 Cbus

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