P89LPC970FDH datasheet(32/66 Pages) NXP

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P89LPC97X_2

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Product data sheet

Rev. 02 — 27 April 2010

32 of 66

NXP Semiconductors

P89LPC970/971/972

8-bit microcontroller with accelerated two-clock 80C51 core

7.22.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),

8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored

in RB8 in special function register SCON. The baud rate is variable and is determined by

the Timer 1 overflow rate or the baud rate generator (described in Section 7.22.5 “Baud

rate generator and selection”).

7.22.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data

bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is

transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.

Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is

received, the 9th data bit goes into RB8 in special function register SCON, while the stop

bit is not saved. The baud rate is programmable to either 1

⁄

16 or

⁄

32 of the CPU clock

frequency, as determined by the SMOD1 bit in PCON.

7.22.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8

data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable

and is determined by the Timer 1 overflow rate or the baud rate generator (described in

Section 7.22.5 “Baud rate generator and selection”).

7.22.5 Baud rate generator and selection

The P89LPC970/971/972 enhanced UART has an independent baud rate generator. The

baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0

SFRs which together form a 16-bit baud rate divisor value that works in a similar manner

as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be

used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 7). Note

that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent baud rate generators use OSCCLK.

7.22.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)

is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is

logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up

when SMOD0 is logic 0.

Fig 7.

Baud rate sources for UART (Modes 1, 3)

baud rate modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

timer 1 overflow

(PCLK-based)

baud rate generator

(CCLK-based)

002aaa897

÷2

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