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P89LPC913 bảng dữ liệu(PDF) 45 Page - NXP Semiconductors |
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P89LPC913 bảng dữ liệu(HTML) 45 Page - NXP Semiconductors |
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45 / 66 page ![]() P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 28 September 2007 45 of 66 NXP Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 8.20 Analog comparators Two analog comparators are provided on the P89LPC912/913/914. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. Comparator 1 may be output to a port pin. The overall connections to both comparators are shown in Figure 21. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. 8.21 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref(bg), is 1.23 V ± 3%. 8.22 Comparator interrupt Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt. Possible comparator configurations are shown in Figure 22. Fig 21. Comparator input and output connections (P0.4) CIN1A (P0.5) CMPREF (P0.2) CIN2A CMF1 CMF2 CN1 CN2 CO1 OE1 CMP1 (P0.6) EC 002aaa496 Vref(bg) comparator 1 comparator 2 interrupt change detect change detect |
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