LPC3230 datasheet(2/73 Pages) NXP

2 / 73 page

LPC3220_30_40_50_1

Preliminary data sheet

Rev. 01 — 6 February 2009

2 of 73

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

I External memory controller for DDR and SDR SDRAM as well as for static devices.

I Two NAND ﬂash controllers: One for single-level NAND ﬂash devices and the other for

multi-level NAND ﬂash devices.

I Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting

74 interrupt sources.

I Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be

used with the SD card port, the high-speed UARTs, I2S-bus interfaces, and SPI

interfaces, as well as memory-to-memory transfers.

I Serial interfaces:

N 10/100 Ethernet MAC with dedicated DMA Controller.

N USB interface supporting either device, host (OHCI compliant), or On-The-Go

(OTG) with an integral DMA controller and dedicated PLL to generate the required

48 MHz USB clock.

N Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One

of the standard UART’s supports IrDA.

N Three additional high-speed UARTs intended for on-board communications that

support baud rates up to 921 600 when using a 13 MHz main oscillator. All

high-speed UARTs provide 64 byte FIFOs.

N Two SPI controllers.

N Two SSP controllers.

N Two I2C-bus interfaces with standard open-drain pins. The I2C-bus interfaces

support single master, slave, and multi-master I2C-bus conﬁgurations.

N Two I2S-bus interfaces, each with separate input and output channels. Each

channel can be operated independently on three pins, or both input and output

channels can be used with only four pins and a shared clock.

I Additional peripherals:

N LCD controller supporting both STN and TFT panels, with dedicated DMA

controller. Programmable display resolution up to 1024

× 768.

N Secure Digital (SD) memory card interface, which conforms to the SD Memory

Card Speciﬁcation Version 1.01.

N General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24

GP output pins, and 51 GP I/O pins.

N 10 bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing from

three pins. Optionally, the ADC can operate as a touch screen controller.

N Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator.

NXP implemented the RTC in an independent on-chip power domain so it can

remain active while the rest of the chip is not powered. The RTC also includes a

32 byte scratch pad memory.

N 32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timer

includes one external capture input pin and a capture connection to the RTC clock.

Interrupts may be generated using three match registers.

N Six enhanced timer/counters which are architecturally identical except for the

peripheral base address. Two capture inputs and two match outputs are pinned out

to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all

four match outputs, timer 4 has one match output, and timer 5 has no inputs or

outputs.

N 32-bit millisecond timer driven from the RTC clock. This timer can generate

interrupts using two match registers.

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