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CS8415A-CSZ bảng dữ liệu(PDF) 23 Page - Cirrus Logic

tên linh kiện CS8415A-CSZ
Giải thích chi tiết về linh kiện  96 kHz Digital Audio Interface Receiver
PDF  46 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8415A-CSZ bảng dữ liệu(HTML) 23 Page - Cirrus Logic

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DS470F4
23
CS8415A
normally occupied by the P bit is used to indicate the location of the block start, SDOUT pin only, serial audio
output port clock must be derived from the AES3 receiver recovered clock)
SOJUST - Justification of SDOUT data relative to OLRCK
Default = ‘0’
0 - Left-justified
1 - Right-justified (master mode only)
SODEL - Delay of SDOUT data relative to OLRCK, for left-justified data formats
Default = ‘0’
0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge
1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge
SOSPOL - OSCLK clock polarity
Default = ‘0’
0 - SDOUT sampled on rising edges of OSCLK
1 - SDOUT sampled on falling edges of OSCLK
SOLRPOL - OLRCK clock polarity
Default = ‘0’
0 - SDOUT data is for the left channel when OLRCK is high
1 - SDOUT data is for the right channel when OLRCK is high
8.5
Interrupt 1 Status (07h) (Read Only)
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since
the register was last read. A ”0” means the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be “0” in this register. This register defaults to 00h.
OSLIP - Serial audio output port data slip interrupt
When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source,
This bit will go high every time a data sample is dropped or repeated.
DETC - D to E C-buffer transfer interrupt.
Indicates the completion of a D to E C-buffer transfer. See “Channel Status and User Data Buffer Manage-
ment” on page 38 for more information.
RERR - A receiver error has occurred.
The Receiver Error register may be read to determine the nature of the error which caused the interrupt.
7
6
5
4
3
210
0
OSLIP
0
0
0
DETC
0
RERR



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