ADC1213D datasheet(13/41 Pages) NXP

13 / 41 page

ADC1213D_SER_5

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Preliminary data sheet

Rev. 05 — 23 April 2010

13 of 41

NXP Semiconductors

ADC1213D series

13. SPI timing

[1]

Typical values measured at VDDA =3V, VDDD = 1.8 V, Tamb =25 °C. Minimum and maximum values are across the full temperature

range Tamb = −40 °C to +85 °C at VDDA =3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM,INBM) = −1 dBFS; internal reference mode;

100

Ω differential applied to serial outputs; unless otherwise specified.

14. Application information

14.1 Analog inputs

14.1.1 Input stage description

The analog input of the ADC1213D supports differential or single-ended input drive.

Optimal performance is achieved using differential inputs with the common-mode input

voltage (VI(cm)) on pins INxP and INxM set to 0.5VDDA.

The full scale analog input voltage range is configurable between

± 1 V (p-p) and

± 2 V (p-p) via a programmable internal reference (see Section 14.2 and Table 21 for

further details).

Figure 6 shows the equivalent circuit of the sample and hold input stage, including

ElectroStatic Discharge (ESD) protection and circuit and package parasitics.

Table 8.

Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Serial Peripheral Interface timings

tw(SCLK)

SCLK pulse width

tw(SCLKH)

SCLK HIGH pulse width

tw(SCLKL)

SCLK LOW pulse width

tsu

set-up time

data to SCLKH

CS to SCLKH

hold time

data to SCLKH

CS to SCLKH

fclk(max)

maximum clock frequency

MHz

Fig 5.

SPI timings

tsu

SDIO

SCLK

R/W

A12

A11

tsu

tw(SCLK)

005aaa065

tw(SCLKL)

tw(SCLKH)

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