ADC1213D datasheet(21/41 Pages) NXP

21 / 41 page

ADC1213D_SER_5

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Preliminary data sheet

Rev. 05 — 23 April 2010

21 of 41

NXP Semiconductors

ADC1213D series

14.5 JESD204A serializer

14.5.1 Digital JESD204A formatter

The block placed after the ADC cores is used to implement all functionalities of the

JESD204A standard. This ensures signal integrity and guarantees the clock and the data

recovery at the receiver side.

The block is highly parameterized and can be configured in various ways depending on

the sampling frequency and the number of lanes used.

Fig 20. CML output connection to the receiver in AC coupling

CMLPA/CMLPB

CMLNA/CMLNB

12 mA to 26 mA

100

10 nF

005aaa083

VDDD

−

RECEIVER

Fig 21. General overview of the JESD204A serializer

FRAME

OCTETS

F octets

SCRAMBLER

TX transport layer

CF: position of controls bits

HD: frame boundary break

Padding with Tails bits (TT)

Mx(N'xS) bits

Lx(F) octets

L octets

N' = N+CS

S samples per frame cycle

samples stream to

lane stream mapping

N bits from Cr0 +

CS bits for control

N bits from CrM−1 +

CS bits for control

M CONVERTERS

L LANES

LANE1

FRAME

OCTETS

F octets

SCRAMBLER

8-bit/

10-bit

SER

TX CONTROLLER

LANE0

8-bit/

10-bit

SER

ALIGNMENT

CHARACTER

GENERATOR

ALIGNMENT

CHARACTER

GENERATOR

SYNC~

005aaa084

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