TMX320C6720RFP300 datasheet(78/118 Pages) TI

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4.13.2 McASP Electrical Data/Timing

4.13.2.1 Multichannel Audio Serial Port (McASP) Timing

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

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Table 4-24 and Table 4-25 assume testing over recommended operating conditions (see Figure 4-29 and

Figure 4-30).

Table 4-24. McASP Timing Requirements(1)(2)

NO.

MIN

MAX

UNIT

Cycle time, AHCLKR external, AHCLKR input

tc(AHCKRX)

Cycle time, AHCLKX external, AHCLKX input

Pulse duration, AHCLKR external, AHCLKR input

7.5

tw(AHCKRX)

Pulse duration, AHCLKX external, AHCLKX input

7.5

Cycle time, ACLKR external, ACLKR input

greater of 2P or 20 ns

tc(ACKRX)

Cycle time, ACLKX external, ACLKX input

greater of 2P or 20 ns

Pulse duration, ACLKR external, ACLKR input

tw(ACKRX)

Pulse duration, ACLKX external, ACLKX input

Setup time, AFSR input to ACLKR internal

Setup time, AFSX input to ACLKX internal

Setup time, AFSR input to ACLKR external input

tsu(AFRXC-ACKRX)

Setup time, AFSX input to ACLKX external input

Setup time, AFSR input to ACLKR external output

Setup time, AFSX input to ACLKX external output

Hold time, AFSR input after ACLKR internal

Hold time, AFSX input after ACLKX internal

Hold time, AFSR input after ACLKR external input

th(ACKRX-AFRX)

Hold time, AFSX input after ACLKX external input

Hold time, AFSR input after ACLKR external output

Hold time, AFSX input after ACLKX external output

Setup time, AXRn input to ACLKR internal

tsu(AXR-ACKRX)

Setup time, AXRn input to ACLKR external input

Setup time, AXRn input to ACLKR external output

Hold time, AXRn input after ACLKR internal

th(ACKRX-AXR)

Hold time, AXRn input after ACLKR external input

Hold time, AXRn input after ACLKR external output

(1)

ACLKX internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

ACLKR internal – ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1

ACLKR external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)

P = SYSCLK2 period

Peripheral and Electrical Specifications

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