74ALVC32_2

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 02 — 10 December 2007

3 of 13

NXP Semiconductors

74ALVC32

Quad 2-input OR gate

5.2 Pin description

6.

Functional description

[1]

H = HIGH voltage level

L = LOW voltage level

7.

Limiting values

[1]

The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2]

[3]

For SO14 packages: above 70

°C derate linearly with 8 mW/K.

For TSSOP14 packages: above 60

°C derate linearly with 5.5 mW/K.

For DHVQFN14 packages: above 60

°C derate linearly with 4.5 mW/K.

Table 2.

Pin description

Symbol

Pin

Description

nA

1, 4, 9, 12

data input

nB

2, 5, 10, 13

data input

nY

3, 6, 8, 11

data output

14

supply voltage

GND

7

ground (0 V)

Table 3.

Function table[1]

Input nA

Input nB

Output nY

LLL

LH

H

HL

H

HHH

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

−0.5

+4.6

V

input clamping current

−50

-

mA

input voltage

−0.5

+4.6

V

output clamping current

-

±50

mA

output voltage

output HIGH or LOW state

[1] [2]

−0.5

V

output 3-state

−0.5

+4.6

V

[2]

−0.5

+4.6

V

output current

-

±50

mA

supply current

-

100

mA

ground current

−100

-

mA

storage temperature

−65

+150

°C

total power dissipation

[3]

-

500

mW