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X25320PI bảng dữ liệu(PDF) 5 Page - Xicor Inc. |
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X25320PI bảng dữ liệu(HTML) 5 Page - Xicor Inc. |
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5 / 15 page ![]() X25320 5 Figure 1. Read E2PROM Array Operation Sequence Operational Notes The X25320 powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. • SO pin is high impedance. • The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes: • The “write enable” latch is reset upon power-up. • A WREN instruction must be issued to set the “write enable” latch. • CS must come HIGH at the proper clock count in order to start a write cycle. Figure 2. Read Status Register Operation Sequence 0123456789 10 20 21 22 23 24 25 26 27 28 29 30 76543210 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 16 BIT ADDRESS 15 14 13 3210 3063 ILL F03 0123456789 10 11 12 13 14 76543210 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 3063 ILL F04 |
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