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WM8731 bảng dữ liệu(PDF) 6 Page - Wolfson Microelectronics plc |
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WM8731 bảng dữ liệu(HTML) 6 Page - Wolfson Microelectronics plc |
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6 / 56 page ![]() WM8731 Advanced Information WOLFSON MICROELECTRONICS LTD AI Rev 2.0 February 2001 6 PIN CONFIGURATION ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE XWM8731EDS -10 to +70 oC 28-pin SSOP 1 AVDD 2 AGND 3 MICBIAS 4 VMID 5 MICIN 6 RLINEIN 7 LLINEIN 8 DCVDD 9 MODE 10 CSB SDIN SCLK XTO XTI/MCLK 15 CLKOUT DGND ADCLRC ADCDAT DACDAT DACLRC BCLK DBVDD LHPOUT HPGND HPVDD RHPOUT LOUT ROUT 11 12 13 14 16 17 18 19 20 21 22 23 24 25 28 27 26 PIN DESCRIPTION PIN NAME TYPE DESCRIPTION 1 DBVDD Supply Digital Buffers VDD 2 CLKOUT Digital Output Buffered Clock Output 3 BCLK Digital Input/Output Digital Audio Bit Clock, Pull Down, (see Note 1) 4 DACDAT Digital Input DAC Digital Audio Data Input 5 DACLRC Digital Input/Output DAC Sample Rate Left/Right Clock, Pull Down (see Note 1) 6 ADCDAT Digital Output ADC Digital Audio Data Output 7 ADCLRC Digital Input/Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1) 8 HPVDD Supply Headphone VDD 9 LHPOUT Analogue Output Left Channel Headphone Output 10 RHPOUT Analogue Output Right Channel Headphone Output 11 HPGND Ground Headphone GND 12 LOUT Analogue Output Left Channel Line Output 13 ROUT Analogue Output Right Channel Line Output 14 AVDD Supply Analogue VDD 15 AGND Ground Analogue GND 16 VMID Analogue Output Mid-rail reference decoupling point 17 MICBIAS Analogue Output Electret Microphone Bias 18 MICIN Analogue Input Microphone Input (AC coupled) 19 RLINEIN Analogue Input Right Channel Line Input (AC coupled) 20 LLINEIN Analogue Input Left Channel Line Input (AC coupled) 21 MODE Digital Input Control Interface Selection, Pull Up (see Note 1) 22 CSB Digital Input 3-Wire MPU Chip Select/ 2-Wire MPU interface address selection, active low, Pull up (see Note 1) 23 SDIN Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input 24 SCLK Digital Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input 25 XTI/MCLK Digital Input Crystal Input or Master Clock Input (MCLK) 26 XTO Digital Output Crystal Output 27 DCVDD Supply Digital Core VDD 28 DGND Ground Digital GND Note: 1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power. |
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