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WM8722 bảng dữ liệu(PDF) 17 Page - Wolfson Microelectronics plc |
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WM8722 bảng dữ liệu(HTML) 17 Page - Wolfson Microelectronics plc |
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17 / 23 page ![]() Advanced Information WM8722 WOLFSON MICROELECTRONICS LTD AI Rev 1.5 May 2000 17 REGISTER 0/1 DAC OUTPUT ATTENUATION A digital attenuator is provided to allow the levels of DAC signals to be attenuated in the digital domain. Register 0 (A[1:0] = 00) is used to control left channel attenuation. Bits 0-7 (AL[7:0]) are used to determine the attenuation level. The level of attenuation is given by: Attenuation = [20.log10 (Attenuation_Data/255)] dB Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set to 0, attenuation data will be loaded into AL[7:0], but it will not affect the attenuation level until LDL is set to 1. LDR in register 1 has the same function for right channel attenuation. Attenuation levels are controlled by setting the register set AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels are given in Table 7. AX[7:0] ATTENUATION LEVEL 00h - ∞ dB (Mute) 01h -48.16 dB :: :: :: FEh -0.034 dB FFh 0dB Table 7. Attenuation Control Levels Register 1 (A[1:0] = 01)is used to control right channel attenuation in a similar manner. REGISTER 2 SOFT MUTE Soft mute is controlled by setting bit 0 in register 2 (A[1:0]=10). A high level on bit 0 will cause the DAC outputs to be muted, the effect of which is to ramp the signal down in the digital domain so that there is no discernible click. DIGITAL DE-EMPHASIS Bit 1 (DE) in register 2 (A[1:0]=10) is used to control digital de-emphasis. A low level on bit 1 disables de-emphasis whilst a high level enables de-emphasis. POWER OFF CONTROL Bit 2 (PWD) in register 2 is used for operation control. With PWD = low (default) the device functions normally. With PWD = high the device is disabled and the outputs are held at midrail. Current consumption of the digital section is minimised, but analogue bias sections remain active in order to preserve DC levels. INPUT WORD RESOLUTION Bits 3 and 4 of register 2 (IW[1:0]) are used to determine the input word resolution. The WM8722 supports 16-bit, 18-bit, 20-bit and 24-bit word formats. BIT 4 (IW1) BIT 3 (IW0) INPUT RESOLUTION 00 16-bit Data Word 01 20-bit Data Word 10 24-bit Data Word 11 18-bit Data Word Table 8. Input Data Resolution |
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