WM8170 datasheet(37/41 Pages) WOLFSON

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WM8170

Product Preview Rev 1.0

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 March 2000

APPLICATIONS RECOMMENDATIONS

SETTING UP THE WM8170 FOR BLACK LEVEL CORRECTION

The WM8170 requires that certain register bits are set in order to get the best performance from the

WM8170, and so that all the Black Level Clamp features within the device are enabled. To help with

this task, the following is a list of register bits that must be set, and what function the bit performs.

Set Reference Select, Address 17Hex (010111Bin) to 01Hex.

V357=1:

This will set the VRT-VRB voltage to 0.75Volts, which will give the best

analogue performance from the WM8170.

Set DC Correct Control, Address 0FHex (011111Bin) to 07Hex.

ACON[10]=00

Area Pulse Generator turned off.

STPIIR=0

The INTBLCENB pulse can be steered to the IIR Filter

STPANAL=0

The INTBLCENB pulse can be steered to the Analogue Loop Enable.

PGAUPD=0

Steer the INTBLCENB pulse to the Analoguee Control Loop on every

frame.

ENVD=1

Enable the Vertical Drive CCD timing signal (VD) operation. VD needs

to be connected to the PDB/VD pin (No. 30).

ENHD=1

Enable the Horizontal Drive CCD timing signal (HD) operation. HD

needs to be connected to the PBLK/HD pin (No. 26).

ENINTBLC=1

Control the Analogue Black Level Clamp from the INTBLCENB

steering circuitry rather than from the BLCENB pin.

Set Analogue Enable Delay, Address 11Hex (010001Bin) to 04Hex.

ANDEL[7:0]=04

The Analogue Correction circuitry will be enabled 4 lines after the

falling edge of the VD signal.

Set Analogue Enable Width, Address 12Hex (010010Bin) to 06Hex.

ANLINE[7:0]=06

The Analogue Correction Circuitry will be enabled for 6 lines.

Set INTBLCENB Delay, Address 13Hex (010011Bin) to 10Hex.

CLPDEL[7:0]=10

The INTBLCENB pulse will be enabled 17 (16+1) pixels after the falling

edge of the BLCENB pin.

Set INTBLCENB Width, Address 14Hex (010100Bin) to 10Hex.

LINDEL[7:0]=10

The INTBLCENB pulse will be enabled for 16 pixels.

Set IIR Filter Coefficient, Address 1EHex (011110Bin) to 04Hex.

COEFF[2:0]=04

IIR Filter Coefficient set to 9, giving 30.1dB attenuation of the noise

during the optically black pixels. This is the middle Filter Coefficient.

The device is now set up to use the internal black level circuitry. The Area Circuitry is not enabled or

programmed at this time.

To enable debug of the signals, the PTDO pin has to be programmed and monitored with an

oscilloscope. The oscilloscope should display VD, HD, BLCENB, PTDO, SHD, SHP. The

oscilloscope should be triggered by VD.

Set Set-Up Register 2, Bits 7, 6, and 5 to 100Bin.

PTDO[2:0]=100

The Analogue DC Loop Enable Pulse is output onto the PTDO pin.

The oscilloscope should show 6 negative going INTBLCENB pulses,

occurring 4 lines after the falling edge of the VD signal. Each

INTBLCENB pulse will be 16 pixels wide, occurring 17 pixels after the

falling edge of the BLCENB signal.

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