WM8170 datasheet(18/41 Pages) WOLFSON

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WM8170

Product Preview Rev 1.0

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 March 2000

INPUT SIGNAL AMPLITUDE

The PGA gain setting allows the WM8170 to amplify the input video signal to be equal to the full-

scale input of the ADC. The minimum input video signal that can be scaled to the full-scale input of

the ADC is defined when the PGA is at the maximum gain. The maximum input video signal that can

be scaled to the full-scale input of the ADC is defined when the PGA is at minimum gain.

The minimum and maximum video input signal, which the WM8170 can accommodate, is set by a

combination of the TIMES2 and the V375 control bits. The input video conditions are summarised in

Table 1

TIMES2

V375

MAXIMUM VIN FOR FULL SCALE

ADC INPUT

PGA GAIN = 00(HEX)

MINIMUM VIN FOR FULL SCALE

ADC INPUT

PGA GAIN = FF(HEX)

1.0V

40mV

1.5V

60mV

0.5V

20mV

0.75V

30mV

Table 1 Input Signal Amplitude Conditions

ANALOGUE TO DIGITAL CONVERTER, DEVICE LATENCY AND OUTPUT TIMING

The 10-bit resolution ADC uses a pipelined architecture. The latency is the time delay between the

video sample (SHD) occurring and the corresponding valid output data being available. There are two

possible inputs that control the detailed timing of data output from the WM8170. These are SHD and

DCLK. The selection between SHD and DCLK is dependent on the control bit RETIME. If RETIME is

set low, then the output data on the D[9:0] pins is referenced to the rising edge of the SHD control

input. If RETIME is set high, the output data on the D[9:0] pins is reference to the rising edge of the

DCLK clock input. The use of RETIME allows the user to accurately control the output data timing,

which can ease the design of the interface between the WM8170 and following digital ASIC,

especially for high pixel rate systems.

With RETIME set low, the WM8170 latency is equal to eight pixel periods. With RETIME set high, the

WM8170 latency is equal to eight pixel periods plus the difference in timing between SHD and DCLK.

These two conditions are shown in Figure 14.

VIDEO

VIDEO SAMPLE,

SHD

REFERENCE

SAMPLE, SHP

D[9:0], RETIME=0

8 PIXEL PERIODS

DCLK

D[9:0], RETIME=1

V10

V11

V12

V13

Figure 14 WM8170 Latency

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