WM8141CFTSLASHV datasheet(25/31 Pages) WOLFSON

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Production Data

WM8141

WOLFSON MICROELECTRONICS LTD

PD Rev 3.0 October 2000

BIT

NAME(S)

DEFAULT

DESCRIPTION

VSMPDET

0 = Normal operation, signal on VSMP input pin is applied directly to Timing

Control block.

1 = Programmable VSMP detect circuit is enabled. An internal

synchronisation pulse is generated from signal applied to VSMP input pin

and is applied to Timing Control block.

3:1

VDEL[2:0]

000

When VSMPDET = 0 these bits have no effect.

When VSMPDET = 1 these bits set a programmable delay from the

detected edge of the signal applied to the VSMP pin. The internally

generated pulse is delayed by VDEL MCLK periods from the detected edge.

See Figure 16 Internal VSMP Pulses Generated by Programmable VSMP

Detect Circuit, for details.

Setup

POSNNEG

When VSMPDET = 0 this bit has no effect.

When VSMPDET = 1 this bit controls whether positive or negative edges

are detected:

0 = Negative edge on VSMP pin is detected and used to generate internal

timing pulse.

1 = Positive edge on VSMP pin is detected and used to generate internal

timing pulse.

See Figure 15 for further details.

Setup

3:0

SELDIS[3:0]

Selective power disable register - activated when SELPD = 1.

Each bit disables respective function when 1, enabled when 0.

SELDIS[0] = Red CDS, PGA

SELDIS[1] = Green CDS, PGA

SELDIS[2] = Blue CDS, PGA

SELDIS[3] = ADC

Table 7 Register Control Bits

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