WM8141

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 3.0 October 2000

6

ANALOGUE CHARACTERISTICS (3.3V OPERATION)

Test Conditions

°C, MCLK = 8MHz unless otherwise stated.

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Overall System Specification Including CDS, PGA, OFFSET and ADC Functions.

Full-scale input voltage range

(see Note 1)

Max Gain

Min Gain

0.2

2.04

Vp-p

Vp-p

Input signal limits (see Note 2)

0

AVDD

V

Full-scale transition error

Gain = 0dB;

PGA[7:0] = 4B(hex)

20

mV

Zero-scale transition error

Gain = 0dB;

PGA[7:0] = 4B(hex)

20

mV

Differential non-linearity

DNL

0.5

LSB

Integral non-linearity

INL

2

LSB

Channel to channel gain matching

1%

References

Upper reference voltage

VRT

1.625

1.725

1.825

V

Lower reference voltage

VRB

0.900

0.975

1.050

V

Input return bias voltage

VRX

0.60

0.65

0.70

V

Diff. reference voltage (VRT-VRB)

0.65

0.75

0.85

V

Output resistance VRT, VRB, VRX

1

Ω

VRLC/Reset-Level Clamp (RLC)

RLC switching impedance

140

Ω

VRLC short-circuit current

5mA

VRLC output resistance

2

Ω

VRLC Hi-Z leakage current

<0.1

µA

RLCDAC resolution

4bits

RLCDAC step size, RLCDAC = 0

0.16

V/step

RLCDAC step size, RLCDAC = 1

0.09

V/step

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 0

0.25

V

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 1

0.2

V

RLCDAC output voltage at

code F(hex), RLCDACRNG = 0

2.75

V

RLCDAC output voltage at

code F(hex), RLCDACRNG = 1

1.7

V

Offset DAC

Resolution

8bits

Differential non-linearity

DNL

0.1

LSB

Integral non-linearity

INL

0.25

LSB

Step size

1.02

mV/step

Output voltage

Code 00(hex)

Code FF(hex)

-130

+130

mV

mV

Programmable Gain Amplifier

Resolution

8bits

Gain

]

0

:

7

[

PGA

283

208

−

V/V

Max gain, each channel

7.4

V/V

Min gain, each channel

0.74

V/V

Gain error, each channel

1%

Notes: 1.

Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.

2.

Input signal limits are the limits within which the full-scale input voltage signal must lie.