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WM8141 bảng dữ liệu(PDF) 2 Page - Wolfson Microelectronics plc |
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WM8141 bảng dữ liệu(HTML) 2 Page - Wolfson Microelectronics plc |
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2 / 31 page  WM8141 Production Data WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 2 PIN CONFIGURATION ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM8141CFT/V 0 to 70 °C 32-pin TQFP OP[2] OP[8] OP[7] OP[6] OP[5] OP[4] OP[3] OP[9] SDI/DNA VRLC/VBIAS BINP GINP RINP OEB SEN/STB VRX 1 8 7 6 5 4 3 2 16 9 10 11 12 13 14 15 24 17 18 19 20 21 22 23 25 32 31 30 29 28 27 26 PIN DESCRIPTION PIN NAME TYPE DESCRIPTION 1 OP[2] Digital output 2 OP[3] Digital output 3 OP[4] Digital IO 4 OP[5] Digital IO 5 OP[6] Digital IO 6 OP[7] Digital IO 7 OP[8] Digital IO 8 OP[9] Digital IO 9 OP[10] Digital IO 10 OP[11]/ SDO Digital IO Hi-Z digital 12-bit bi-directional bus. There are several modes: Hi-Z: when OEB = 1. 12-bit output: 12-bit data is output on OP[11:0]. 8-bit multiplexed output: data is output on OP[11:4] at 2 ∗ ADC conversion rate. 6-bit multiplexed output: data is output on OP[11:6] at 2 ∗ ADC conversion rate. 4-bit multiplexed output: data is output on OP[11:8] at 4 ∗ ADC conversion rate. Input 8-bit: control data is input on OP[11:4] in parallel mode when SCK/RNW = 0, and SEN/STB = 0. Output 8-bit: register read back data is output in parallel on OP[11:4] when SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1. 11 NRESET Digital input Reset input, active low. This signal forces a reset of all internal registers and selects whether the serial or parallel control bus is used (see SEN/STB). 12 AVDD Supply Analogue supply (3.3/5V) for CDS, PGA and OFFSET blocks. This must be operated at the same potential as DVDD1. 13 AGND Supply Analogue ground (0V). 14 DVDD1 Supply Digital supply (3.3/5V) for logic and clock generator. This must be operated at the same potential as AVDD. 15 VRB Analogue output Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. 16 VRT Analogue output Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. 17 VRX Analogue output Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. 18 VRLC/ VBIAS Analogue IO Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. 19 BINP Analogue input Blue channel input video. 20 GINP Analogue input Green channel input video. 21 RINP Analogue input Red channel input video. 22 OEB Digital input Output Hi-Z control: all outputs disabled when OEB = 1. |
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