VG3617801CT datasheet(17/68 Pages) VML

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Document:1G5-0133

Rev.1

Page 17

VIS

VG3617801CT

16Mb CMOS Synchronous Dynamic RAM

7.PRECHARGE

The PRECHARGE command can be asserted anytime after tRAS(min) is satisfied.

Soon after the PRECHARGE command is asserted, PRECHARGE operation is performed. The synchronous DRAM

enters the idle state after tRP(min) is satisfied. The parameter tRP is the time required to perform the PRECHARGE.

The earliest timing in a READ cycle that a PRECHARGE command can be asserted without losing any data in the

burst is as followed.

PRECHARGE

In order to write all data to the memory cell correctly, the asynchronous parameter”tDPL” must be satisfied.

The tDPL(MIN.) specification defines the earliest time that a PRECHARGE command can be asserted after a WRITE

cycle. The minimum number of clocks are calculated by dividing tDPL(min.) by the clock cycle time.

In summary, the PRECHARGE command can be asserted relative to the reference clock of the last valid

data. In the following table, minus means clocks before the reference, plus means time after the reference.

CAS latency

READ

WRITE

-1

+tDPL(min.)

-2

+tDPL(min)

Burst lengh=4

CLK

Command

CAS latency=2

Command

CAS latency=3

CAS latency= 2: One clock earlier than the last output data.

3: Two clocks earlier than the last output data.

(tRAS is satisfied)

Hi-Z

PRE

Read

PRE

Hi-Z_

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